FIGS. 17(a)-17(d) are cross-sectional views illustrating a method of fabricating a prior art high frequency high output semiconductor device having a plated heat sink (referred to as PHS hereinafter) layer on a rear surface of a semiconductor chip disclosed in Japanese Published Patent Application No. Hei 6-209058. First, after a photoresist 4 having an opening in a chip separating region is formed on the surface of a semiconductor substrate 1 where a plurality of semiconductor elements are formed, the semiconductor substrate 1 is etched by reactive ion etching (RIE) or the like using the photoresist as a mask, thereby forming a chip separating groove 2 of a depth of 25-30 .mu.m. Meanwhile, the etching proceeds not only in the depth direction but also in the lateral direction to some degree, resulting in an etching 3 under the photoresist. Next, the metallization layer 5 is disposed on the entire surface of the wafer using vacuum evaporation or sputtering deposition (FIG. 17(a)). Next, by removing the photoresist 4, the metallization layer 5 is left only on the internal surface of the chip separation groove 2. This is easily accomplished because of the under cut 3. Next, after the resist 44 is formed on the surface of the semiconductor substrate except the chip separating groove, the plating layer 55 of a thickness of about 5 .mu.m is formed only inside the chip separating groove by electrolytic plating using the metallization layer 5 as an electrical supply layer (FIG. 17(b)). This plating layer is to keep these semiconductor chips mechanically joined after the semiconductor substrate is separated into semiconductor chips by polishing the rear surface of the substrate, which will be described later, and a thickness of about 5 .mu.m is required as described above. Next, the surface of the semiconductor substrate 1 is adhered to the glass plate 7 using the wax 6 (FIG. 17(c)). Furthermore, the semiconductor substrate 1 is polished on the rear surface side until the bottom of the metallization layer is exposed (FIG. 17(d)). The thickness of the semiconductor substrate 1 is thus made 25-30 .mu.m which is almost the same as the depth of the chip separating groove, whereby the semiconductor substrate is separated into the semiconductor chips. Next, after a PHS layer comprising Au of 40-50 .mu.m thickness is formed on the entire surface of the rear surface side of the semiconductor substrate 1, the glass plate 7 is removed from the semiconductor substrate 1 by removing the wax 6 and the wafer is washed. Furthermore, the surface of the PHS layer opposite the semiconductor substrate side is adhered to an expand film and dicing is performed. That is, the wafer is cut at the PHS layer in the chip separating groove region with a dicing blade.
Using the fabricating method described above, the semiconductor device comprising the semiconductor chip having a semiconductor element formed on its front surface and the PHS layer formed on its rear surface is obtained. This PHS layer is a heat dispersing body for dispersing heat produced in the semiconductor element such as a field effect transistor or the like formed on the surface of the semiconductor chip. This PHS layer also simplifies handling of the thin semiconductor substrate after the removal of the glass plate or the semiconductor chip after dicing.
In the above fabricating method, when the chip separating groove 2 is formed using RIE, the peripheral region of the front surface of the semiconductor substrate 1 is shielded by a susceptor ring or the like which holds the substrate, and the chip separating groove is not formed in this region. Because of this shielding, the plating layer in this region becomes a plating protrusion on the front surface of the semiconductor substrate in the subsequent plating layer formation process. If the glass plate is adhered to the substrate surface with the wax in this condition, a crack lc occurs in the semiconductor substrate under the plating protrusion 555 as illustrated in FIG. 18. And, even for the region where the chip separating groove 2 is properly formed and the metallization layer 5 and the plating layer 55 are formed on the internal surface of the chip separating groove 2, in a step of polishing the rear surface of the semiconductor substrate until the bottom of the metallization layer 5 is exposed, the chip separating groove, which is deeper than other chip separating grooves, is polished even after the bottom of the metallization layer 5 is exposed, resulting in the rupture 5d of the metallization layer 5 and the further rupture 55a of the plating layer 55 as shown in FIG. 19. Even in a case in which these ruptures do not occur, as the metallization layer 5 protrudes from the polished rear surface of the semiconductor substrate, a subsequent photolithography process becomes very difficult. Furthermore, burrs are produced at a section of the PHS layer (protrusion of the PHS layer toward the rear surface side of the semiconductor substrate) in the dicing process (step of cutting the PHS layer). These burrs fully protrude from the rear surface of the PHS layer and this considerably deteriorates the adhesion between the PHS layer and a chip carrier, degrading heat conduction from the PHS layer to the chip carrier.
As a fabricating method of a semiconductor device which is intended to avoid the above difficulties, the fabricating method disclosed in U.S. Pat. No. 5,275,958 is devised. This method is described as follows. FIGS. 20(a)-20(h) are cross-sectional views illustrating this method in the processing order. First, after the surface protection film 200 is formed on the region of the front surface of the semiconductor substrate 1 which is about 600 .mu.m thickness where semiconductor elements are formed, the first chip separating groove 2 of a depth of 5-15 .mu.m is formed on the front surface of the semiconductor substrate 1 by etching (FIG. 20(a)). Next, the first chip separating groove plating layer 51 of a thickness of about 10 .mu.m and comprising Au is formed inside this first chip separating groove 2 (FIG. 20(b)), and the glass plate 7 is attached to the front surface of the semiconductor substrate 1 by the wax 6 (FIG. 20(c)). Furthermore, by etching the rear surface of the semiconductor substrate 1 in a region opposite to the first chip separating groove 2 until the bottom of the first chip separating groove plating layer 51 is exposed, the second chip separating groove 22 is formed (FIG. 20(d)). Next, the photoresist 8 is formed on the rear surface of the semiconductor substrate 1 except the region of the second chip separating groove 22 and, using this photoresist as a mask, the second chip separating groove plating layer 52 of a thickness of about 10 .mu.m and comprising Au is formed inside the second chip separating groove 22 (FIG. 20(e)). Furthermore, after the photoresist 8 is removed, the semiconductor substrate 1 is thinned to a thickness of 20-30 .mu.m by polishing the rear surface of the substrate. When the substrate is thinned, since the second chip separating groove plating layer 52 is also polished simultaneously, the structure where the second chip separating groove plating layer 52 is formed only inside the second chip separating groove 22 which is left after the polishing as illustrated in FIG. 20(f) is obtained. Next, the PHS layer 10 of a thickness of 40-60 .mu.m is formed on the rear surface of the semiconductor substrate 1 except for the region of the second chip separating groove 22 (FIG. 20(g)). Then, by melting and removing the wax 6, the glass plate 7 is removed from the semiconductor substrate 1, and the surface of the PHS layer 10 opposite the semiconductor substrate side is adhered to the dicing tape 300. Finally, by cutting the first and the second chip separating groove plating layers, the semiconductor device comprising the semiconductor chip having a semiconductor element formed on its front surface and the PHS layer formed on its rear surface is obtained (FIG. 20(h)). Although the burrs 52a (portion of the plating layer bending toward the rear surface side of the semiconductor substrate in the figure) are produced in the cutting process, these burrs do not protrude from the surface of the PHS layer opposite the semiconductor substrate side, and consequently, the adhesion between the PHS layer and a chip carrier becomes excellent in a subsequent step of mounting the semiconductor device onto the chip carrier.
In this fabricating method, the polishing of the rear surface of the semiconductor substrate is performed after the second chip separating groove 22 and the second chip separating groove plating layer 52 are formed. However, in the United States Patent, a method in which the second chip separating groove 22 and the second chip separating groove plating layer 52 are formed after the polishing of the rear surface of the semiconductor substrate is performed is also disclosed. In this case, the first chip separating groove 2 formed on the front surface of the semiconductor substrate is of such a depth that it does not penetrate to the rear surface of the semiconductor substrate as a result of the polishing of the rear surface of the semiconductor substrate.
In the fabricating method disclosed in the United States Patent, since the bottom surface of the first chip separating groove plating layer does not appear on the polishing surface when the rear surface of the semiconductor substrate is polished, the metallization layer or the plating layer inside the chip separating groove is not ruptured, nor does it protrude from the rear surface of the semiconductor substrate as in the fabricating method described first.
In the fabricating method of a semiconductor device disclosed in the United States Patent, the first chip separating groove plating layer has a thickness of 10 .mu.m, which is thicker than that of the plating layer in the groove of the fabricating method described first, which is 5 .mu.m. This is because a PHS layer is not formed in the region of the rear surface of the semiconductor substrate where the first and the second chip separating grooves are formed and, therefore, it is necessary to maintain the strength of the mechanical connection between semiconductor chips only with the plating layer inside the chip separating grooves. However, even in the method disclosed in this United States Patent, the occurrence of a crack in the semiconductor substrate due to the plating protrusion cannot be prevented.
Furthermore, in the fabricating method disclosed in the United States Patent, since the PHS layer is not formed in the region of the rear surface of the semiconductor substrate where the first and the second chip separating grooves are formed, the strength of the mechanical connection between semiconductor chips is weaker than that in a case where the PHS layer is formed on the entire rear surface of the semiconductor substrate including the chip separating groove region as in the fabricating method described first. Therefore, after the PHS layer is formed and the glass plate is removed, handling is difficult when the semiconductor chips are joined in the shape of the semiconductor substrate, and measurement of electrical characteristics of the semiconductor element at this stage also becomes difficult.